The Industry Council on ESD Target Levels is an independent body of ESD experts with the mission to review the ESD robustness requirements of modern IC products for allowing safe handling and mounting in an ESD protected area.
The current scope has been further expanded to provide recommendations for next generation qualification target levels for human body model (HBM) and charged device model (CDM) in accordance with the ESDA Technology Roadmap, while also taking into account both state-of-the-art IC design and manufacturing constraints.
Additionally, the Council is addressing critically needed goals for industry alignments in defining methods to mitigate electrical over-stress (EOS) and recommending efficient system level IEC ESD design and realistic test practices.
The Industry Council (on ESD Target Levels) was established in 2006 when a few IC companies decided to understand why often during the product qualification process, at every corporation, passing the ESD test is a frequent bottleneck for customer acceptance. The pattern was the same when an IC product fails to meet the historically accepted ESD requirements, leading to several design cycles in order to meet the specified ESD expectations, and at the same time the task becoming more and more time consuming as the technologies advance. Simultaneous to this, most companies had the experience that for different reasons multiple products were supplied to the market that did not meet the same ESD requirements. No one observed reliability problems with these products. The ad hoc Council thus embarked on a mission to re-examine and establish safe and practical ESD levels that are necessary for manufacturing and the target levels that will have minimum impact on circuit performance requirements.
The original participants included Infineon, Texas Instruments, Philips (now NXP), Barth Electronics, Thermo-Keytek (now Thermo-Fisher Scientific), and Sarnoff-Europe (now SOFICS). What started as a small group that met in Belgium to brainstorm on how to approach the ESD qualification issues has now after five years expanded into a worldwide body of 40+ members representing IC suppliers, consultants, contractors, advisers, foundries, as well as some customers. Many in the industry were confused in the beginning if this is a new standardization body. Soon it became clear that the Council consists of individual experts who represent their own companies in conducting studies for the common cause and for interacting with the standardization bodies such as JEDEC and ESDA. The purpose of the Council is to make recommendations through publications of white papers.
The mission of the Industry Council on ESD Target Levels is essentially to review the ESD robustness requirements of modern IC products for allowing safe handling and mounting in an ESD protected area. While accommodating both the capability of the manufacturing sites and the constraints posed by the downscaled process technologies on practical protection designs, the Council's purpose is to provide consolidated recommendations for future ESD target levels. The Council Members and Associates are to promote these recommended targets to be adopted as company goals. Being an independent institution, the Council presents the results and supportive data to all interested standardization bodies. With this original mission, the Council has produced two key white papers [1, 2] on HBM/MM and CDM requirements, during 2007 and 2008 respectively. The papers were also published as JEDEC documents JEP155 (HBM) and JEP157 (CDM).
These papers have eventually set in motion a realistic view of the required ESD levels for modern IC production. The major conclusions were that as long as all basic ESD control methods, which are mandatory for IC manufacturing and handling, are followed: 1) HBM levels between 500V to 2kV are equally safe for qualification, 2) CDM levels of minimum 250V are safe and lower than this requires more detailed control implementation at the production sites, and 3) MM is a redundant test while meeting the HBM/CDM test provides sufficient protection for IC handling and productions. Both of these papers have been accepted by the ESDA Board and the JEDEC Board and are now available as public documents.
The nature of the IC industry dictates that circuit performance and reliability are both of paramount importance while the market demands can result in the former overriding the latter. Fortunately in the case of ESD component level requirements it has been demonstrated by the Council that there is plenty of safe margin that allows the ESD levels to be reduced without reliability consequences. Collection of extensive data and evaluation of modern factory mandatory control methods have established that new ESD levels (500V or greater for HBM and 250V or greater for CDM) allow safe manufacturing and are compatible for IC designs to achieve data rates exceeding 15 Gb/Sec. High performance components e.g. in the internet applications dictate these new levels to be adopted.
Another aspect of much misunderstanding in the industry concerns the requirements for system level ESD protection and its coupling with component level requirements. For example, some IC customers commonly believe that requiring high levels of HBM protection (like for example, 8kV) would essentially protect the systems to achieve ESD protection defined by the IEC test at 8 kV. The purposes of testing under these two models vastly differ and a more realistic approach is needed to efficiently design for system level ESD. The Council has more recently published a new white paper  to not only clarify these misconceptions but also point to a more desired approach for system level ESD protection design strategy that takes into consideration the chip functions (such as HDMI, USB, Ethernet, etc.). The third white paper was also published as a JEDEC document JEP161.The conclusions from this white paper are: 1) requiring high levels of HBM or CDM would not protect at system level, and 2) the optimum strategy for system level protection requires communication between the supplier and the system designer to realize a co-design concept of printed circuit board (PCB) and IC. Based on adequate component level ESD (which is safe if the minimum necessary levels discussed above are met) the clear attention must be for protecting the entire system on a PCB. To this effect, the Council is now in the process of writing an extension of White Paper 3 examining the full details as well as the nuances of system level ESD that include EMC and EMI considerations.
The Council is very fortunate to have not only eager participation from dedicated experts but also excellent support from the member organizations' managements. The support and encouragement of the ESD Association and JEDEC organization is the key to make credible changes that have impact and acceptance. As the Council alludes, with the advancement towards sub-50 nm technologies realistic and efficient ESD will be the new vogue. The Council is now proposing a roadmap for component ESD levels for advances to 22nm and beyond. The ESDA is using these inputs to announce an ESD technology roadmap  that calls for attention to much better factory control methods to be adopted.
Trough this article we are appealing to the industry to come together to make ESD as a common problem for the customer, the supplier, and the consultant alike. The unprecedented initiative taken by the Council we hope will have long lasting impact. If anyone is interested in joining the Council for this common cause they are encouraged to contact the Council chairs.