Last Updated on Friday, May 14, 2021 01:44
CDM has become the primary real-world ESD event metric describing ESD charging and rapid discharge events in automated handling, manufacturing, and assembly of IC devices. Its importance has dramatically increased over the years as package feature sizes, capacitance, and pin count have scaled upward. In years past, arbitrary CDM protection levels had been specified as IC qualification goals with little background information available on actual/realistic CDM event levels and the protection methods available in manufacturing controls and device design for the safe production of IC components. The rapid advancement of IC technology scaling, coupled with the increased demand for high-speed circuit performance, made it increasingly difficult to guarantee a customer-specified “500 volts” CDM specification and as this update will discuss, even 250 volts can create challenges. At the same time, the required static control methods available for production area CDM protection at each process step have not been fully outlined. Therefore, a realistic CDM specification target must be defined in terms of available and commonly practiced CDM control methods and must reflect current ESD design constraints. Additionally, as technology scaling continues, very high-speed I/Os are being introduced which demand the need for lower CDM target levels in order to achieve the needed I/O performance. This is the scope of this latest update to White Paper 2.
By balancing improved static ESD controls specific to CDM, and limited ESD design capability in today’s leading technologies, we recommend a CDM specification target level of 250 volts with consideration for lower CDM target levels in unique cases where very high-speed I/O performance is needed. These target levels are a realistic and safe CDM level for manufacturing and handling today’s products using basic CDM control methods, or advanced CDM control techniques as needed based on the target level.
At the same time, we show that the current trend of silicon technology scaling will continue to place further restrictions on achievable CDM levels. It is, therefore, necessary that the Industry Council presents a realistic CDM roadmap for consideration by the industry moving forward to 7 nm technologies and beyond, including 2.5D and 3D technologies.