Introduction to Latch-up and Standards Timeline
After publishing white papers on target levels for human body model (HBM), charged device model (CDM), system level electrostatic discharge (ESD), and the elimination of MM testing the Industry Council on ESD Target Levels recognized the effectiveness of this organization for addressing fundamental reliability issues facing the electronics industry. This led to the publication of a white paper on Electrical Overstress (EOS) which has brought increased clarity to the understanding of EOS and the need for cooperation between suppliers and users of integrated circuits for understanding the causes and solutions to EOS issues. In light of these successes, the Council has addressed the issue of latch-up and latch-up testing by performing a survey of industry experience with latch-up and latch-up testing. This white paper is a report on the finding of that survey.
Latch-up, which is the triggering of a parasitic low-ohmic path between power supply rails that can either damage the integrated circuit (IC) or make the IC inoperable, has been described since the late 1960s. Latch-up became a reliability concern in the mid-80s [3], leading to the first standard document JESD17. The first practical Industry IC latch-up testing method with injection current requirement, JESD78, was published in the mid-90s by JEDEC and has been revised five times by the JESD78 Working Group. Subsequent revisions brought improvements, clarifications, and different trigger conditions, as illustrated in Figure 1.
At the time this survey was conducted, latch-up standard JESD78E was in effect and used for most latch-up testing. However, JESD78F was in the ballot process at that time. JESD78F was approved and issued in early 2022. JESD78F is a substantial rewrite of JESD78E intended to make the standard easier to understand and deal with the challenges of applying latch-up testing to a wide variety of integrated circuits functioning over a wide range of voltages. It is important to understand however that the basic latch-up testing requirements in JESD78F are fundamentally the same as in JESD78E. In this white paper, references to the “current”, “present”, or “existing” JEDEC standard are referring to JESD78E unless otherwise specified.
The I/O test method essentially tests latch-up robustness by trying to inject a ±100 mA current with a clamping voltage applied to the pin. This will lead to substrate currents that may, for example, trigger a parasitic thyristor in an I/O or an internal buffer.
For various reasons, including technology scaling, increasing amounts of integration, and the complexity and variety of semiconductor components, the standard has faced challenges addressing the needs of the increasingly diverse semiconductor product space. Some of those challenges include:
Survey Report Organization
These challenges have prompted the Industry Council on ESD Target Levels to re-evaluate the existing latch-up standard, JESD78E, in today’s context. Throughout this document definitions of terms like e.g., injection current and MSV, are used as described in JESD78E. To understand more on how the Industry is dealing with the topic and to get more information on how the Industry uses latch-up testing results and to understand what Industry expects from latch-up testing, the Industry Council on ESD Targets has set up a concise, yet detailed survey.
Some of the major questions that this survey is trying to answer include:
The goal of this survey is to provide clarification on the test execution and use of the testing results and to derive recommendations, based on the data collected from a wide audience, for future directions of the JESD78 standard and potentially other standards. The data analysis and the recommendations are presented in this report. The response summary is available in Appendix C.
For better readability, Chapter 2 (“Detailed Analysis of the Survey”) is split into different parts. We do this by following the same order of individual sections as used in the survey, which is:
Chapter 3 then summarizes the findings and provides recommendations for future work.
(Click Here for full Revision 1.0 PDF of White Paper 5) - 5.0MB