Last Updated on Monday, February 1, 2021
Industry Council Survey on Latch-up
[THIS SURVEY IS NOW CLOSED]
Latch-up, which is the triggering of a low-ohmic path between power supply rails that can either damage the IC or make the IC inoperable, became a reliability concern in the mid 80's. The first practical Industry IC latch-up testing method with injection current requirement, JESD78, was published in the mid 90's by JEDEC and has been revised five times by the JESD78 Working Group. Some more info is available here.
For various reasons including technology scaling, increasing amounts of integration, and the complexity and variety of semiconductor components, the standard has faced challenges addressing the needs of the increasingly diverse semiconductor product space. Some of those challenges are:
- It is unclear how this test method correlates to real threats.
- In many low-voltage cases, the current injected in the IO is very limited.
- There are many technicalities that can disqualify a result. Examples are the active state of the DUT, the definition of special pins and power supply instability.
This has prompted the Industry Council on ESD Target Levels, working with the JESD78 Working Group, to re-evaluate the latch-up standard in today's context. To understand more on how people are dealing with the topic and to get more information on how the Industry uses latch-up testing results and to understand what industry expects from latch-up testing, the Industry Council has set up a survey.
Please check back with us for updates and results.
For reference, a full pdf version of the survey is also available.